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Disambiguation of "Choi, Kiyoung"

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Hybrid spiking-stochastic Deep Neural Network.

, , and . VLSI-DAT, page 1-4. IEEE, (2017)

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Andreas Choi

Chiwon Choi

Jinsub Choi

Bongkyung Choi

Carmen Choi

 

Other publications of authors with the same name

Lower-bits cache for low power STT-RAM caches., and . ISCAS, page 480-483. IEEE, (2012)Optimal mapping of program overlays onto many-core platforms with limited memory capacity., , and . Des. Autom. Embed. Syst., 21 (3-4): 173-194 (2017)Binary acceleration using coarse-grained reconfigurable architecture., , and . SIGARCH Comput. Archit. News, 38 (4): 33-39 (2010)A new stochastic mutiplier for deep neural networks., , and . ISOCC, page 46-47. IEEE, (2017)Energy Efficient Analog Synapse/Neuron Circuit for Binarized Neural Networks., , and . ISOCC, page 271-272. IEEE, (2018)Exploiting Early Partial Reconfiguration of Run-Time Reconfigurable FPGAs in Embedded Systems Design., , and . FPGA, page 247. ACM, (1999)Entry control in network-on-chip for memory power reduction., , and . ISLPED, page 171-176. ACM, (2008)Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems., and . CASES, page 230-237. ACM, (2004)Coarse-grained reconfigurable architecture for multiple application domains: a case study., , , , , , and . ICHIT, volume 321 of ACM International Conference Proceeding Series, page 546-553. ACM, (2009)Critical-path-aware high-level synthesis with distributed controller for fast timing closure., and . ACM Trans. Design Autom. Electr. Syst., 19 (2): 16:1-16:29 (2014)