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Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells., , , , , , , , , и 4 other автор(ы). J. Parallel Distributed Comput., 74 (6): 2484-2496 (2014)A Discussion on Test Pattern Generation for FPGA - Implemented Circuits., , , , и . J. Electron. Test., 17 (3-4): 283-290 (2001)DCG-FGT transistor: Retention study of Floating Gate charge., , , , , и . MWSCAS, стр. 825-827. IEEE, (2013)Elucidating 1S1R operation to reduce the read voltage margin variability by stack and programming conditions optimization., , , , , , , , , и 4 other автор(ы). IRPS, стр. 1-6. IEEE, (2021)A Self-referenced and regulated sensing solution for PCM with OTS selector., , , , , , и . VLSI-SoC, стр. 1-6. IEEE, (2021)1S1R sub-threshold operation in Crossbar arrays for low power BNN inference computing., , , , , , , , , и 10 other автор(ы). IMW, стр. 1-4. IEEE, (2022)Improvement of a VCO concept for low energy particule detection and recognition., , , , и . LATW, стр. 1-4. IEEE, (2014)Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study., , , и . ETW, стр. 146-151. IEEE Computer Society, (1999)A High-Speed Structural Method for Testing Address Decoder Faults in Flash Memories., , и . ITC, стр. 1-10. IEEE Computer Society, (2008)Minimizing the Number of Test Configurations for Different FPGA Families., , , и . Asian Test Symposium, стр. 363-368. IEEE Computer Society, (1999)