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CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off.

, , , , , , , и . ISCA, стр. 666-679. IEEE, (2020)

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Daniel Lois

Lois Hoegl

Christos Lois

Lois Hopfgartner

Gertraude Loisch-Langer

 

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ITAP: Idle-Time-Aware Power Management for GPU Execution Units., , , , , , , , , и . ACM Trans. Archit. Code Optim., 16 (1): 3:1-3:26 (2019)DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks., , , , , , , и . CoRR, (2021)BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows., , , , , , , , , и 2 other автор(ы). HPCA, стр. 345-358. IEEE, (2021)Architecting a computer with a full optical RAM., , и . ICECS, стр. 716-719. IEEE, (2016)Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration., , , , , , , , , и . MICRO, стр. 298-311. IEEE Computer Society, (2018)Temporal frequent value locality., и . ASAP, стр. 147-152. IEEE Computer Society, (2016)CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off., , , , , , , и . ISCA, стр. 666-679. IEEE, (2020)IChannels: Exploiting Current Management Mechanisms to Create Covert Channels in Modern Processors., , , , , , , и . ISCA, стр. 985-998. IEEE, (2021)D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput., , , , и . HPCA, стр. 582-595. IEEE, (2019)FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching., , , , , , , , , и 1 other автор(ы). MICRO, стр. 313-328. IEEE, (2020)