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Genetic Algorithm-Based Energy-Aware CNN Quantization for Processing-In-Memory Architecture., , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 11 (4): 649-662 (2021)Compute-in-Memory: From Device Innovation to 3D System Integration., , , , , , , and . ESSDERC, page 21-28. IEEE, (2021)A Runtime Reconfigurable Design of Compute-in-Memory based Hardware Accelerator., , , , and . DATE, page 932-937. IEEE, (2021)Machine Learning Assisted Statistical Variation Analysis of Ferroelectric Transistors: From Experimental Metrology to Predictive Modeling., , , , , , , , , and 1 other author(s). VLSI Technology and Circuits, page 336-337. IEEE, (2022)DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Training., , , , and . CoRR, (2020)NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark., , , , and . Frontiers Artif. Intell., (2021)DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (11): 2306-2319 (2021)Design of Non-volatile Capacitive Crossbar Array for In-Memory Computing., , , , and . IMW, page 1-4. IEEE, (2021)A Cross-layer Framework for Design Space and Variation Analysis of Non-Volatile Ferroelectric Capacitor-Based Compute-in-Memory Accelerators., , , and . ASPDAC, page 159-164. IEEE, (2024)NeuroSim Validation with 40nm RRAM Compute-in-Memory Macro., , , , and . AICAS, page 1-4. IEEE, (2021)