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A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application.

, , , and . DATE, page 1136-1141. IEEE Computer Society, (2005)

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Efficient Signal Reconstruction via Distributed Least Square Optimization on a Systolic FPGA Architecture., , , , and . ICASSP, page 1493-1497. IEEE, (2019)Learning to Walk: Spike Based Reinforcement Learning for Hexapod Robot Central Pattern Generation., , , and . AICAS, page 208-212. IEEE, (2020)XBAROPT - Enabling Ultra-Pipelined, Novel STT MRAM Based Processing-in-Memory DNN Accelerator., , , and . AICAS, page 36-40. IEEE, (2020)Energy-Recovery Techniques to Reduce On-Chip Power Density in Molecular Nanotechnologies., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 52-I (8): 1580-1589 (2005)A 65nm 376nA 0.4V linear classifier using time-based matrix-multiplying ADC with non-linearity aware training., and . A-SSCC, page 309-312. IEEE, (2017)A Survey of FPGA-Based Robotic Computing., , , , , , , and . CoRR, (2020)OPTIMO: A 65-nm 279-GOPS/W 16-b Programmable Spatial-Array Processor with On-Chip Network for Solving Distributed Optimizations via the Alternating Direction Method of Multipliers., , , and . IEEE J. Solid State Circuits, 55 (3): 629-638 (2020)MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles., , , , , , , and . CoRR, (2021)EM-X-DL: Efficient Cross-device Deep Learning Side-channel Attack With Noisy EM Signatures., , , , , and . ACM J. Emerg. Technol. Comput. Syst., 18 (1): 4:1-4:17 (2022)A 65nm 60mW Dual-Loop Adaptive Digital Beamformer with Optimized Sidelobe Cancellation and On-Chip DOA Estimation for mm-Wave Applications., , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)