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Selective DRAM cache bypassing for improving bandwidth on DRAM/NVM hybrid main memory systems.

Y. Ro, M. Sung, Y. Park, and J. Ahn. IEICE Electron. Express, 14 (11): 20170437 (2017)

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Bora Ro

Seonhi Ro

Bjong-Ro Kim

Hea-Kyung Ro

Mee-Yoen Ro

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Enforcing Last-Level Cache Partitioning through Memory Virtual Channels.J. Chung, Y. Ro, J. Kim, J. Ahn, J. Kim, J. Kim, J. Lee, and J. Ahn. PACT, page 97-109. IEEE, (2019)Reducing memory access latency with asymmetric DRAM bank organizations.Y. Son, S. O, Y. Ro, J. Lee, and J. Ahn. ISCA, page 380-391. ACM, (2013)SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture.Y. Son, H. Cho, Y. Ro, J. Lee, and J. Ahn. IEEE Comput. Archit. Lett., 16 (1): 76-79 (2017)Aquabolt-XL HBM2-PIM, LPDDR5-PIM With In-Memory Processing, and AXDIMM With Acceleration Buffer.J. Kim, S. Kang, S. Lee, H. Kim, Y. Ro, S. Lee, D. Wang, J. Choi, J. So, Y. Cho and 4 other author(s). IEEE Micro, 42 (3): 20-30 (2022)Leveraging Power-Performance Relationship of Energy-Efficient Modern DRAM Devices.S. Lee, H. Cho, Y. Son, Y. Ro, N. Kim, and J. Ahn. IEEE Access, (2018)Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond.J. Kim, S. Kang, S. Lee, H. Kim, W. Song, Y. Ro, S. Lee, D. Wang, H. Shin, B. Phuah and 10 other author(s). HCS, page 1-26. IEEE, (2021)Selective DRAM cache bypassing for improving bandwidth on DRAM/NVM hybrid main memory systems.Y. Ro, M. Sung, Y. Park, and J. Ahn. IEICE Electron. Express, 14 (11): 20170437 (2017)SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures.Y. Ro, H. Cho, E. Lee, D. Jung, Y. Son, J. Ahn, and J. Lee. HPCA, page 517-528. IEEE Computer Society, (2017)25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications.Y. Kwon, S. Lee, J. Lee, S. Kwon, J. Ryu, J. Son, S. O, H. soo Yu, H. Lee, S. Kim and 20 other author(s). ISSCC, page 350-352. IEEE, (2021)Understanding power-performance relationship of energy-efficient modern DRAM devices.S. Lee, Y. Ro, Y. Son, H. Cho, N. Kim, and J. Ahn. IISWC, page 110-111. IEEE Computer Society, (2017)

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Disambiguation of "Ro, Yuhwan"

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Selective DRAM cache bypassing for improving bandwidth on DRAM/NVM hybrid main memory systems.

Please choose a person to relate this publication to

Bora Ro

Seonhi Ro

Bjong-Ro Kim

Hea-Kyung Ro

Mee-Yoen Ro

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Ro, Yuhwan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Selective DRAM cache bypassing for improving bandwidth on DRAM/NVM hybrid main memory systems.

Please choose a person to relate this publication to

Bora Ro

Seonhi Ro

Bjong-Ro Kim

Hea-Kyung Ro

Mee-Yoen Ro

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Selective DRAM cache bypassing for improving bandwidth on DRAM/NVM hybrid main memory systems.