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A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics., , , , , , , , , и 4 other автор(ы). ESSCIRC, стр. 463-466. IEEE, (2021)A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process., , , , , , , , , и 18 other автор(ы). CICC, стр. 1-2. IEEE, (2022)A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme., , , , , , , , , и 9 other автор(ы). ISSCC, стр. 44-46. IEEE, (2012)A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application., , , , , , , , , и 13 other автор(ы). VLSI Technology and Circuits, стр. 148-149. IEEE, (2022)A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power., , , , , , , , , и 20 other автор(ы). ISSCC, стр. 378-380. IEEE, (2019)Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices., , , , , , , , , и 2 other автор(ы). HPCA, стр. 61-72. IEEE Computer Society, (2017)A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking., , , , , , , , , и 13 other автор(ы). ISSCC, стр. 496-498. IEEE, (2011)22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process., , , , , , , , , и 29 other автор(ы). ISSCC, стр. 382-384. IEEE, (2020)Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM., , , , , , , , , и 25 other автор(ы). A-SSCC, стр. 153-156. IEEE, (2017)SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures., , , , , , и . HPCA, стр. 517-528. IEEE Computer Society, (2017)