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Disambiguation of "Jeong, Deog-Kyoon"

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A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS.

, , and . ISCAS, page 1869-1872. IEEE, (2014)

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Su-Jeong Jeong

Wonrae Jeong

Hyung-Gon Jeong

Hang-Kyun Jeong

Chang-Kyo Jeong

 

Other publications of authors with the same name

A theoretical analysis of phase shift in pulse injection-locked oscillators., , , , , and . ISCAS, page 1662-1665. IEEE, (2016)A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop., , , , and . A-SSCC, page 73-76. IEEE, (2018)A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control., , and . CICC, page 1-4. IEEE, (2017)A Fully Integrated 700MA Event-Driven Digital Low-Dropout Regulator with Residue-Tracking Loop for Fine-Grained Power Management Unit., and . VLSI Circuits, page 231-232. IEEE, (2018)A 0.015-mm2 Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (6): 655-659 (2017)A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Reduced Variation of Decision Threshold Voltage., , , , , and . IEEE J. Solid State Circuits, 55 (8): 2219-2227 (2020)A 2.4-GHz 0.25-μm CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 39 (7): 1185-1190 (2004)Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector., , , , and . IEEE J. Solid State Circuits, 57 (10): 3014-3024 (2022)A Maximum-Eye-Tracking CDR With Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (12): 2708-2720 (2020)A Practical Implementation of IEEE 1588-2008 Transparent Clock for Distributed Measurement and Control Systems., and . IEEE Trans. Instrumentation and Measurement, 59 (2): 433-439 (2010)