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Maestro: A Memory-on-Logic Architecture for Coordinated Parallel Use of Many Systolic Arrays.

, , , , and . ASAP, page 42-50. IEEE, (2019)

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Packing Sparse Convolutional Neural Networks for Efficient Systolic Array Implementations: Column Combining Under Joint Optimization., , and . CoRR, (2018)Saturation RRAM Leveraging Bit-Level Sparsity Resulting from Term Quantization., , and . ISCAS, page 1-5. IEEE, (2021)Sparse Coding Trees with application to emotion classification., , , and . CVPR Workshops, page 77-86. IEEE Computer Society, (2015)Systolic Building Block for Logic-on-Logic 3D-IC Implementations of Convolutional Neural Networks., , , , , , , , , and . ISCAS, page 1-5. IEEE, (2019)Dynamic Patch Sampling for Efficient Training and Dynamic Inference in Vision Transformers., and . ICMLA, page 83-89. IEEE, (2023)StitchNet: Composing Neural Networks from Pre-Trained Fragments., , , and . ICMLA, page 61-68. IEEE, (2023)BranchyNet: Fast inference via early exiting from deep neural networks., , and . ICPR, page 2464-2469. IEEE, (2016)PNNU: Parallel Nearest-Neighbor Units for Learned Dictionaries., , and . LCPC, volume 9519 of Lecture Notes in Computer Science, page 223-237. Springer, (2015)Accelerating Vision Transformer Training via a Patch Sampling Schedule., and . CoRR, (2022)Term quantization: furthering quantization at run time., , and . SC, page 96. IEEE/ACM, (2020)