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FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability., , , , , , and . ICSAMOS, page 149-156. IEEE, (2009)User-Level DMA without Operating System Kernel Modification., and . HPCA, page 322-331. IEEE Computer Society, (1997)VLSI micro-architectures for high-radix crossbar schedulers., , and . NOCS, page 217-224. ACM/IEEE Computer Society, (2011)The Next Generation of Exascale-Class Systems: The ExaNeSt Project., , , , , , , , , and 8 other author(s). DSD, page 510-515. IEEE Computer Society, (2017)Building an FoC Using Large, Buffered Crossbar Cores., , and . IEEE Des. Test Comput., 25 (6): 538-548 (2008)On-chip communication and synchronization mechanisms with cache-integrated network interfaces., , , and . Conf. Computing Frontiers, page 217-226. ACM, (2010)Towards Exascale: Measuring the Energy Footprint of Astrophysics HPC Simulations., , , , , , , , , and 2 other author(s). eScience, page 403-412. IEEE, (2019)RED-SEA: Network Solution for Exascale Architectures., , , , , , , , , and 58 other author(s). DSD, page 712-719. IEEE, (2022)A Vector Hardware Accelerator with Circuit Simulation Emphasis., , , , , , , , and . DAC, page 89-94. IEEE Computer Society Press / ACM, (1987)A Systematic Evaluation of Emerging Mesh-like CMP NoCs., , , , , , and . ANCS, page 159-170. IEEE Computer Society, (2015)