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Exploiting the Potentials of the Second Generation SX-Aurora TSUBASA.

, , , , , , и . PMBS@SC, стр. 39-49. IEEE, (2020)

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Ryusuke Shimada

Yuko Egawa

Masashi Egawa

Kazuko Pfeiffer-Egawa

 

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Foreword., и . IEICE Trans. Electron., 106 (6): 301-302 (июня 2023)A power-aware shared cache mechanism based on locality assessment of memory reference for CMPs., , , и . MEDEA@PACT, стр. 113-120. ACM, (2007)Modeling of cache access behavior based on Zipf's law., , , и . MEDEA@PACT, стр. 9-15. ACM, (2008)Performance Evaluation of a Next-Generation SX-Aurora TSUBASA Vector Supercomputer., , , , , , и . ISC, том 13948 из Lecture Notes in Computer Science, стр. 359-378. Springer, (2023)Design of a 3-D stacked floating-point adder., , и . 3DIC, стр. 1-4. IEEE, (2013)Improving the Accuracy in SpMV Implementation Selection with Machine Learning., , , , и . CANDAR (Workshops), стр. 172-177. IEEE, (2020)A Systolic Memory Architecture for Fast Codebook Design based on MMPDCL Algorithm., , , , и . ITCC (1), стр. 572-578. IEEE Computer Society, (2004)A media-oriented vector architectural extension with a high bandwidth cache system., , , , и . COOL Chips, стр. 1-3. IEEE Computer Society, (2012)A cache partitioning mechanism to protect shared data for CMPs., , , , и . COOL Chips, стр. 1-2. IEEE Computer Society, (2016)Peachy Parallel Assignments (EduHPC 2019)., , , , , , , , , и 2 other автор(ы). EduHPC@SC, стр. 75-83. IEEE, (2019)