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Disambiguation of "Arthur, John V."

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Cognitive computing building block: A versatile and efficient digital neuron model for neurosynaptic cores.

, , , , , , , , , , , , , , , and . IJCNN, page 1-10. IEEE, (2013)

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V Saile

V Geoffroy

V Ustinov

V Fendrich

V Adams

 

Other publications of authors with the same name

A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm., , , , , and . CICC, page 1-4. IEEE, (2011)IBM NorthPole Neural Inference Machine., , , , , , , , , and 22 other author(s). HCS, page 1-58. IEEE, (2023)Truenorth ecosystem for brain-inspired computing: scalable systems, software, and applications., , , , , , , , , and 36 other author(s). SC, page 130-141. IEEE Computer Society, (2016)Real-time sensory information processing using the TrueNorth Neurosynaptic System., , , , , , , , , and 2 other author(s). ISCAS, page 2911. IEEE, (2016)11.4 IBM NorthPole: An Architecture for Neural Network Inference with a 12nm Chip., , , , , , , , , and 22 other author(s). ISSCC, page 214-215. IEEE, (2024)Silicon Neurons that Inhibit to Synchronize., and . ISCAS, page 1186. IEEE, (2007)Discovering Low-Precision Networks Close to Full-Precision Networks for Efficient Inference., , , , , , and . EMC2@NeurIPS, page 6-9. IEEE, (2019)Learning in Silicon: Timing is Everything., and . NIPS, page 75-82. (2005)An in-silico Neural Model of Dynamic Routing through Neuronal Coherence., , , and . NIPS, page 1401-1408. Curran Associates, Inc., (2007)Silicon neurons that inhibit to synchronize., and . ISCAS, IEEE, (2006)