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A Digital Neurosynaptic Core Using Event-Driven QDI Circuits., , , , , and . ASYNC, page 25-32. IEEE Computer Society, (2012)11.4 IBM NorthPole: An Architecture for Neural Network Inference with a 12nm Chip., , , , , , , , , and 22 other author(s). ISSCC, page 214-215. IEEE, (2024)Building block of a programmable neuromorphic substrate: A digital neurosynaptic core., , , , , , , , , and 2 other author(s). IJCNN, page 1-8. IEEE, (2012)A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm., , , , , and . CICC, page 1-4. IEEE, (2011)IBM NorthPole Neural Inference Machine., , , , , , , , , and 22 other author(s). HCS, page 1-58. IEEE, (2023)Self-Timed Thermally-Aware Circuits., , and . ISVLSI, page 438-439. IEEE Computer Society, (2006)Truenorth ecosystem for brain-inspired computing: scalable systems, software, and applications., , , , , , , , , and 36 other author(s). SC, page 130-141. IEEE Computer Society, (2016)Design and Tool Flow of IBM's TrueNorth: an Ultra-Low Power Programmable Neurosynaptic Chip with 1 Million Neurons.. ISPD, page 59-60. ACM, (2016)Variability in 3-D integrated circuits., , , , and . CICC, page 659-662. IEEE, (2008)Cognitive computing building block: A versatile and efficient digital neuron model for neurosynaptic cores., , , , , , , , , and 6 other author(s). IJCNN, page 1-10. IEEE, (2013)