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Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques.

C. Lee, H. Chi, J. Heo, J. Park, J. Jang, D. Lee, J. Jung, D. Lee, D. Kim, K. Kim, S. Kim, D. Park, Y. Lim, G. Park, S. Lee, S. Hong, D. Kwon, I. Hwang, B. Na, K. Kim, S. Choi, H. Choi, Hangi-Jung, W. Bae, J. Ihm, S. Bae, N. Kim, and J. Lee. IEEE J. Solid State Circuits, 56 (1): 212-224 (2021)

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Dae Hyun Kim

Dae-Hyun Yang

Dae-Soon Kim

Yong-Dae Kim

Dae-Uh Kim

Other publications of authors with the same name

HeM3D: Heterogeneous Manycore Architecture Based on Monolithic 3D Vertical Integration.A. Arka, B. Joardar, R. Kim, D. Kim, J. Doppa, and P. Pande. CoRR, (2020)The Effect of Presentation on Visual Working Memory.D. Kim, S. Kim, and K. Han. HCI (26), volume 434 of Communications in Computer and Information Science, page 346-350. Springer, (2014)System level approach for low energy consumption in wireless personal area networks.D. Kim, and K. Bae. ICCE, page 520-521. IEEE, (2016)Analysis of disordered speech signal using wavelet transform.C. Jo, and D. Kim. ICSLP, ISCA, (1998)Classification of pathological voice into normal/benign/malignant state.C. Jo, and D. Kim. EUROSPEECH, page 571-574. ISCA, (1999)Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits.K. Yang, T. Liu, R. Zhang, D. Kim, and L. Milor. Microelectron. Reliab., (2017)Bayesian Optimization over Permutation Spaces.A. Deshwal, S. Belakaria, J. Doppa, and D. Kim. AAAI, page 6515-6523. AAAI Press, (2022)25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM.Y. Kim, H. Kim, J. Choi, M. Ahn, D. Lee, S. Cho, D. Park, Y. Park, M. Jang, Y. Kim and 24 other author(s). ISSCC, page 346-348. IEEE, (2021)Power, Performance, and Thermal Trade-offs in M3D-enabled Manycore Chips.S. Musavvir, A. Chatterjee, R. Kim, D. Kim, J. Doppa, and P. Pande. DATE, page 1752-1757. IEEE, (2020)Small-World Network Enabled Energy Efficient and Robust 3D NoC Architectures.S. Das, D. Lee, D. Kim, and P. Pande. ACM Great Lakes Symposium on VLSI, page 133-138. ACM, (2015)

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Disambiguation of "Kim, Dae-Hyun"

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An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques.

Please choose a person to relate this publication to

Dae Hyun Kim

Dae-Hyun Yang

Dae-Soon Kim

Yong-Dae Kim

Dae-Uh Kim

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Kim, Dae-Hyun"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques.

Please choose a person to relate this publication to

Dae Hyun Kim

Dae-Hyun Yang

Dae-Soon Kim

Yong-Dae Kim

Dae-Uh Kim

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques.