( en | de | ru )

 

Disambiguation of "Mahmoodi-Meimand, Hamid"

Author of the publication

copydeleteadd this publication to your clipboard
Estimation of delay variations due to random-dopant fluctuations in nano-scaled CMOS circuits.

, , and . CICC, page 17-20. IEEE, (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Benjamin Mahmoodi

Mehrdad Mahmoodi

Ahmad Hamidov

Zahra Hamidi

Saeed Hamid-Khani

 

Other publications of authors with the same name

Efficient power clock generation for adiabatic logic., and . ISCAS (4), page 642-645. IEEE, (2001)Dual-edge triggered level converting flip-flops., and . ISCAS (2), page 661-664. IEEE, (2004)A novel synthesis approach for active leakage power reduction using dynamic supply gating., , , , and . DAC, page 479-484. ACM, (2005)Energy recovery clocked dynamic logic., , , and . ACM Great Lakes Symposium on VLSI, page 468-471. ACM, (2005)A Novel Low-Power Scan Design Technique Using Supply Gating., , , , and . ICCD, page 60-65. IEEE Computer Society, (2004)Low power synthesis of dynamic logic circuits using fine-grained clock gating., , , and . DATE, page 862-867. European Design and Automation Association, Leuven, Belgium, (2006)Estimation of delay variations due to random-dopant fluctuations in nano-scaled CMOS circuits., , and . CICC, page 17-20. IEEE, (2004)Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM., , , and . Asian Test Symposium, page 176-181. IEEE Computer Society, (2005)Dual-Edge Triggered Static Pulsed Flip-Flops., and . VLSI Design, page 846-849. IEEE Computer Society, (2005)Data-retention flip-flops for power-down applications., and . ISCAS (2), page 677-680. IEEE, (2004)