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Другие публикации лиц с тем же именем

Efficient power clock generation for adiabatic logic., и . ISCAS (4), стр. 642-645. IEEE, (2001)A novel synthesis approach for active leakage power reduction using dynamic supply gating., , , , и . DAC, стр. 479-484. ACM, (2005)Dual-edge triggered level converting flip-flops., и . ISCAS (2), стр. 661-664. IEEE, (2004)Energy recovery clocked dynamic logic., , , и . ACM Great Lakes Symposium on VLSI, стр. 468-471. ACM, (2005)A Novel Low-Power Scan Design Technique Using Supply Gating., , , , и . ICCD, стр. 60-65. IEEE Computer Society, (2004)Low power synthesis of dynamic logic circuits using fine-grained clock gating., , , и . DATE, стр. 862-867. European Design and Automation Association, Leuven, Belgium, (2006)Data-retention flip-flops for power-down applications., и . ISCAS (2), стр. 677-680. IEEE, (2004)Estimation of delay variations due to random-dopant fluctuations in nano-scaled CMOS circuits., , и . CICC, стр. 17-20. IEEE, (2004)Dual-Edge Triggered Static Pulsed Flip-Flops., и . VLSI Design, стр. 846-849. IEEE Computer Society, (2005)Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM., , , и . Asian Test Symposium, стр. 176-181. IEEE Computer Society, (2005)