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Design of Sequential Circuits in Multilayer QCA Structure.

, , , and . ISED, page 21-25. IEEE Computer Society, (2013)

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Introducing universal QCA logic gate for synthesizing symmetric functions with minimum wire-crossings., , and . ICWET, page 828-833. ACM, (2010)Design and Analysis of Regular Clock Based 2: 4 Decoder Using T-Gate in QCA., , , and . ASCAT, volume 1443 of Advances in Intelligent Systems and Computing, page 81-91. Springer, (2023)Synthesis of Reversible Universal Logic around QCA with Online Testability., , , and . ISED, page 236-241. IEEE Computer Society, (2011)Towards Designing Reliable Universal QCA Logic in the Presence of Cell Deposition Defect., , , , and . VLSID, page 575-576. IEEE Computer Society, (2016)Regular clocking-based Automated Cell Placement technique in QCA targeting sequential circuit., , , , , , and . Comput. Electr. Eng., (2022)Towards modular design of reliable quantum-dot cellular automata logic circuit using multiplexers., , , and . Comput. Electr. Eng., (2015)A Realistic Configurable Level Triggered Flip-Flop in Quantum-Dot Cellular Automata., , and . VDAT, volume 1066 of Communications in Computer and Information Science, page 455-467. Springer, (2019)Design of fault tolerant majority voter for TMR circuit in QCA., , , and . VDAT, page 1-2. IEEE, (2016)A PUF based Light Weight Protocol for Secure WiFi Authentication of IoT devices., , , and . ISED, page 183-187. IEEE, (2018)Design of low power 5-input majority voter in quantum-dot cellular automata with effective error resilience., , and . ISED, page 101-105. IEEE, (2016)