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Disambiguation of "Itoh, Kiyoo"

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Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers.

, , and . ACM Great Lakes Symposium on VLSI, page 529-533. ACM, (2007)

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Naoki Itoh

Itoh Wihardjo Surjono

 

Other publications of authors with the same name

Low-voltage limitations of memory-rich nano-scale CMOS LSIs., , and . ESSCIRC, page 68-75. IEEE, (2007)Low-Voltage Embedded-RAM Technology: Present and Future., and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 277-288. Kluwer, (2001)Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs., , , , and . CICC, page 1-7. IEEE, (2011)Variability-Conscious Circuit Designs for Low-Voltage Memory-Rich Nano-Scale CMOS LSIs.. PATMOS, volume 6448 of Lecture Notes in Computer Science, page 255. Springer, (2010)Energy efficiency optimization for digital applications in 28nm UTBB FDSOI technology., , , , and . MIXDES, page 23. IEEE, (2015)Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era.. ISLPED, page 273-274. ACM, (2009)Memory at VLSI Circuits Symposium., , , and . IEEE J. Solid State Circuits, 43 (4): 762-768 (2008)Adaptive Circuits for the 0.5-V Nanoscale CMOS Era., , and . IEICE Trans. Electron., 93-C (3): 216-233 (2010)Beyond the horizon: The next 10x reduction in power - Challenges and solutions., , , , , , , , , and . ISSCC, page 31. IEEE, (2011)A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-VT sense amplifiers., , and . ISLPED, page 123-126. ACM, (2006)