From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS., , , и . ISSCC, стр. 384-385. IEEE, (2008)Efficient Ising Model Mapping to Solving Slot Placement Problem., , , , , , , и . ICCE, стр. 1-6. IEEE, (2019)Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers., , и . ACM Great Lakes Symposium on VLSI, стр. 529-533. ACM, (2007)Technology/circuits joint evening panel discussion semiconductor industry in 2020: Evolution or revolution?, , , , , , , , , и 3 other автор(ы). VLSIC, стр. 22-. IEEE, (2015)Graph Minors from Simulated Annealing for Annealing Machines with Sparse Connectivity., , , , , , , , , и . TPNC, том 11324 из Lecture Notes in Computer Science, стр. 111-123. Springer, (2018)A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation., , , , , и . CICC, стр. 701-704. IEEE, (2009)Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource Sharing., , , и . Int. J. Netw. Comput., 7 (2): 154-172 (2017)Operating-margin-improved SRAM with column-at-a-time body-bias control technique., и . ESSCIRC, стр. 396-399. IEEE, (2007)A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems., , , , и . A-SSCC, стр. 1-3. IEEE, (2021)An energy-efficient parallel-processing method based on master-hibernating DVFS., и . ISCAS, стр. 1724-1727. IEEE, (2014)