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An Ultra Low-Energy VLSI Approximate Discrete Haar Wavelet Transform for ECG Data Compression., , , , и . ICECS, стр. 1-4. IEEE, (2023)A New Architecture for 2's Complement Gray Encoded Array Multiplier., , и . SBCCI, стр. 14-19. IEEE Computer Society, (2002)Approximate adder synthesis for area- and energy-efficient FIR filters in CMOS VLSI., , и . NEWCAS, стр. 1-4. IEEE, (2015)A power-efficient imprecise radix-4 multiplier applied to high resolution audio processing., , , , и . ICECS, стр. 261-264. IEEE, (2016)Using adder and subtractor compressors to sum of absolute transformed differences architecture for low-power video encoding., , , , , , , и . ICECS, стр. 490-493. IEEE, (2017)Low-Power HEVC 8-point 2-D Discrete Cosine Transform Hardware Using Adder Compressors., , , , , , и . NEWCAS, стр. 309-312. IEEE, (2018)Exploring the combination of number of bits and number of iterations for a power-efficient fixed-point CORDIC implementation., , , и . ICECS, стр. 302-305. IEEE, (2017)Framework-based arithmetic core generation to explore ASIC-based parallel binary multipliers., , , , и . ICECS, стр. 478-481. IEEE, (2017)Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach., , , , , и . ICECS, стр. 859-862. IEEE, (2010)Power efficient architecture for motion estimation using the QSDS-DIC algorithm., , , и . ICECS, стр. 331-334. IEEE, (2009)