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Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technology.

, , and . ISCAS, page 2778-2781. IEEE, (2007)

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Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature., , , , and . PATMOS, page 1-7. IEEE, (2014)Multi-application electrical stimulator architecture dedicated to waveform control by electrode-tissue impedance spectra monitoring., , , and . ICECS, page 33-36. IEEE, (2012)3D Integration for Digital and Imagers Circuits: Opportunities and Challenges.. PATMOS, volume 6448 of Lecture Notes in Computer Science, page 256. Springer, (2010)Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities., , , , , , and . PATMOS, volume 5953 of Lecture Notes in Computer Science, page 266-275. Springer, (2009)A mixed LPDDR2 impedance calibration technique exploiting 28nm Fully-Depleted SOI Back-Biasing., , , and . ICICDT, page 1-4. IEEE, (2012)Energy autonomous sensor systems: Towards a ubiquitous sensor technology., , , , , , , , , and 1 other author(s). Microelectron. J., 41 (11): 740-745 (2010)Computing detection probability of delay defects in signal line tsvs., , , , , , , and . ETS, page 1-6. IEEE Computer Society, (2013)Dedicated network for distributed configuration in a mixed-signal Wireless Sensor Node circuit., , and . PATMOS, page 55-62. IEEE, (2015)Guest Editorial Special Issue on Nanoelectronic Circuit and System Design Methods for the Mobile Computing Era., , , and . JETC, 13 (2): 12:1-12:2 (2016)A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits., , , , and . DATE, page 1056-1057. EDA Consortium San Jose, CA, USA / ACM DL, (2013)