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Internode: Internal Node Logic Computational Model.

, , , , , и . Annual Simulation Symposium, стр. 241-248. IEEE Computer Society, (2003)

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Manuel J A Eugster

Manuel J A Eugster

Manuel J A Eugster

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Heinrich J J Mieschendahl

 

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Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates., , , , , и . PATMOS, том 5349 из Lecture Notes in Computer Science, стр. 389-398. Springer, (2008)New CMOS VLSI linear self-timed architectures., , , , , и . ASYNC, стр. 14-23. IEEE Computer Society, (1995)Multimedia System for Instruction and Learning Electronics., , , и . CALISCE, том 1108 из Lecture Notes in Computer Science, стр. 442-444. Springer, (1996)Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements., , , , , , и . IES, стр. 1-7. IEEE, (2006)Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits., , , , и . PATMOS, том 1918 из Lecture Notes in Computer Science, стр. 316-326. Springer, (2000)Inertial and degradation delay model for CMOS logic gates., , , , и . ISCAS, стр. 459-462. IEEE, (2000)SODS: a new CMOS differential-type structure., , , , и . IEEE J. Solid State Circuits, 30 (7): 835-838 (июля 1995)A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch., , , , , и . ISCAS, стр. 2019-2022. IEEE, (1993)HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model., , , , и . DATE, стр. 467-471. IEEE Computer Society, (2001)Degradation Delay Model Extension to CMOS Gates., , , , и . PATMOS, том 1918 из Lecture Notes in Computer Science, стр. 149-158. Springer, (2000)