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Disambiguation of "Valencia-Barrero, Manuel"

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New CMOS VLSI linear self-timed architectures.

, , , , , and . ASYNC, page 14-23. IEEE Computer Society, (1995)

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Victor Manuel Bastidas Valencia

Alvaro Valencia

William Valencia

Ray Valencia

Meiser Valencia

 

Other publications of authors with the same name

Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits., , , , and . PATMOS, volume 1918 of Lecture Notes in Computer Science, page 316-326. Springer, (2000)Selective Clock-Gating for Low-Power Synchronous Counters., , , and . J. Low Power Electron., 1 (1): 11-19 (2005)Hamming-Code Based Fault Detection Design Methodology for Block Ciphers., , , , , and . ISCAS, page 1-5. IEEE, (2020)Asymmetric clock driver for improved power and noise performances., , , and . ISCAS, page 893-896. IEEE, (2007)Modeling of real bistables in VHDL., , , , and . EURO-DAC, page 460-465. IEEE Computer Society, (1993)Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1., , and . PATMOS, volume 2451 of Lecture Notes in Computer Science, page 448-457. Springer, (2002)New CMOS VLSI linear self-timed architectures., , , , , and . ASYNC, page 14-23. IEEE Computer Society, (1995)Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher., , , , and . DCIS, page 1-6. IEEE, (2018)Fault attack on FPGA implementations of Trivium stream cipher., , and . ISCAS, page 562-565. IEEE, (2016)HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model., , , , and . DATE, page 467-471. IEEE Computer Society, (2001)