( en | de | ru )

 

Disambiguation of "Kim, Jae-Jin"

Author of the publication

copydeleteadd this publication to your clipboard
Experimental Results of Affective Valence and Arousal to Avatar's Facial Expressions.

, , , , , , , , and . Cyberpsychology Behav. Soc. Netw., 8 (5): 493-503 (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jae Jin Kim

Jin Kim

Jin Kim

Jin Kim

Jin Kim

 

Other publications of authors with the same name

A new techology mapping for CPLD under the time constraint., , and . ASP-DAC, page 235-238. ACM, (2001)Deformable model with surface registration for hippocampal shape deformity analysis in schizophrenia., , , , , , , and . NeuroImage, 22 (2): 831-840 (2004)A Low Power Communication Circuit Design Using Selective Glitch Removal Method., , , , and . FGCN (2), page 51-56. IEEE Computer Society, (2008)978-0-7695-3431-2.A CLB-based CPLD Low-power Technology Mapping Algorithm considered a Trade-off., and . J. Inform. and Commun. Convergence Engineering, 5 (1): 59-63 (2007)Learning Dynamic Graph Representation of Brain Connectome with Spatio-Temporal Attention., , and . NeurIPS, page 4314-4327. (2021)Feasibility of a Virtual Reality Program in Managing Test Anxiety: A Pilot Study., , , , , and . Cyberpsychology Behav. Soc. Netw., 23 (10): 715-720 (2020)Experimental Results of Affective Valence and Arousal to Avatar's Facial Expressions., , , , , , , , and . Cyberpsychology Behav. Soc. Netw., 8 (5): 493-503 (2005)Utilizing dynamic parallelism in CUDA to accelerate a 3D red-black successive over relaxation wind-field solver., , , , , and . Environ. Model. Softw., (2021)Aggressive Function Splitting for Partial Inlining., , , and . Interaction between Compilers and Computer Architectures, page 80-86. IEEE Computer Society, (2011)FPGA Low Power Technology Mapping for Reuse Module Design under the Time Constraint., , , and . FGCN (2), page 57-61. IEEE Computer Society, (2008)978-0-7695-3431-2.