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Disambiguation of "Jou, Shyh-Jye"

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A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology.

, , , , , and . SoCC, page 160-164. IEEE, (2014)

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Nabil Al-Jou Jou

Shyh-Yuong Lee

Ren-Jye Shiue

Shyi-Ming Jou

Yuan-jeh Jou

 

Other publications of authors with the same name

A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists., , , , , , , , , and 2 other author(s). SoCC, page 455-462. IEEE, (2014)10Gbps Decision Feedback Equalizer with Dynamic Lookahead Decision Loop., , and . ISCAS, page 1839-1842. IEEE, (2009)Sub-word and reduced-width Booth multipliers for DSP applications., , , , and . ISCAS (3), page 575-578. IEEE, (2002)An IEEE 802.15.3c/802.11ad compliant SC/OFDM dual-mode baseband receiver for 60 GHz Band., , , , , , , , and . ISCAS, page 1006-1009. IEEE, (2014)A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code., , and . ISCAS (5), page 293-296. IEEE, (2004)A Parallel Event-Driven MOS Timing Simulator on Distributed-Memory Multiprocessors., , and . ISCAS, page 574-577. IEEE, (1995)A 40Gb/s All-Digital Adaptive Noise-Suppression Feed-Forward Filter and Adaptive Decision Feedback Equalizer with 40 parallelisms for 2-PAM Systems., , , , and . ISCAS, page 1-4. IEEE, (2018)Digitally-controlled cell-based oscillator with multi-phase differential outputs., and . ASICON, page 610-613. IEEE, (2011)Gb/s prototyping of 60GHz indoor wireless SC/OFDM transmitter and receiver on FPGA demo system., , , , , , and . ICCE-TW, page 204-205. IEEE, (2015)An all digital phase-locked loop with modified binary search of frequency acquisition., , and . ICECS, page 195-198. IEEE, (1998)