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Disambiguation of "Yu, Bei"

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IT-DSE: Invariance Risk Minimized Transfer Microarchitecture Design Space Exploration.

, , , , , , , and . ICCAD, page 1-9. IEEE, (2023)

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Bei Yu

Bei-Bei Yang

Rongxing Bei

Bei Hu

Bei Cheng

 

Other publications of authors with the same name

Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design., , , , , and . DAC, page 70:1-70:6. ACM, (2017)Floorplanning and Topology Generation for Application-Specific Network-on-Chip., , , and . CoRR, (2014)Methodology for standard cell compliance and detailed placement for triple patterning lithography., , , and . CoRR, (2014)Incremental Layer Assignment for Timing Optimization., , , and . ACM Trans. Design Autom. Electr. Syst., 22 (4): 75:1-75:25 (2017)Pushing multiple patterning in sub-10nm: are we ready?, , , , and . DAC, page 197:1-197:6. ACM, (2015)PARR: pin access planning and regular routing for self-aligned double patterning., , , , and . DAC, page 28:1-28:6. ACM, (2015)Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting., , and . CoRR, (2014)Aging-Aware Critical Path Selection via Graph Attention Networks., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (12): 5006-5019 (December 2023)Pin-Accessible Legalization for Mixed-Cell-Height Circuits., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (1): 143-154 (2022)CTM-SRAF: Continuous Transmission Mask-Based Constraint-Aware Subresolution Assist Feature Generation., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (10): 3402-3411 (October 2023)