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Designing asynchronous circuits from behavioural specifications with internal conflicts., , , and . ASYNC, page 106-115. IEEE, (1994)Implementation of a performance optimized database join operation on FPGA-GPU platforms using OpenCL., and . NORCAS, page 1-6. IEEE, (2017)Early Power Estimation for System-on-Chip Designs., , , and . PATMOS, volume 1918 of Lecture Notes in Computer Science, page 108-117. Springer, (2000)Decomposition and technology mapping of speed-independent circuits using Boolean relations., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (9): 1221-1236 (1999)Performance and energy-efficient implementation of a smart city application on FPGAs., , , , , , , , and . J. Real Time Image Process., 17 (3): 729-743 (2020)To Spike or Not to Spike: A Digital Hardware Perspective on Deep Learning Acceleration., , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 13 (4): 1015-1025 (December 2023)Quasi-Static Scheduling of Independent Tasksfor Reactive Systems., , , , and . ICATPN, volume 2360 of Lecture Notes in Computer Science, page 80-100. Springer, (2002)Verification and synthesis of counters based on symbolic techniques., , , and . ED&TC, page 176-181. IEEE Computer Society, (1997)Fast Hardware/Software Co-Simulation for Virtual Prototyping and Trade-Off Analysis., , , and . DAC, page 389-394. ACM Press, (1997)Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems., , , , and . DAC, page 110-115. ACM Press, (1999)