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Disambiguation of "Watanabe, Takamoto"

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An all-digital ADC/TDC for sensor interface with TAD architecture in 0.18-µm digital CMOS.

, and . ICECS, page 219-222. IEEE, (2009)

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Wataru Watanabe

Rie Watanabe

Norihiro Watanabe

Shigeo Watanabe

Shigeo Watanabe

 

Other publications of authors with the same name

All-Digital-Very-Scalable-ADC TAD Showing Scaling-Effect in 40/16nm-CMOS Technology.. ICECS, page 105-108. IEEE, (2018)An all-digital A/D converter TAD with 4-shift-clock construction for sensor interface in 0.65-μm CMOS., and . ESSCIRC, page 178-181. IEEE, (2010)All-digital 0.016mm2 reconfigurable sensor-ADC using 4CKES-TAD in 65nm digital CMOS., , , and . ICECS, page 21-24. IEEE, (2014)All-digital TAD-OFDM detection for sensor interface using TAD-digital synchronous detection., and . ICECS, page 786-789. IEEE, (2010)A 0.0027-mm2 9.5-bit 50-MS/s all-digital A/D converter TAD in 65-nm digital CMOS., , and . ICECS, page 271-274. IEEE, (2009)An all-digital ADC/TDC for sensor interface with TAD architecture in 0.18-µm digital CMOS., and . ICECS, page 219-222. IEEE, (2009)A 28-GHz monolithic integrated quadrature oscillator in SiGe bipolar technology., , and . IEEE J. Solid State Circuits, 38 (1): 135-137 (2003)DC-coupled IF stage design for a 900-MHz ISM receiver., , and . IEEE J. Solid State Circuits, 38 (1): 126-134 (2003)All-Digital VCO-ADC TAD Using 4CKES-Type in 16-nm FinFET CMOS for Technology Scaling With Stochastic-ADC Method.. ICECS, page 1-4. IEEE, (2021)All-Digital VCO-ADC TAD Confirming Scaling and Stochastic Effects Using 16-nm FinFET CMOS.. ICECS, page 1-4. IEEE, (2021)