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Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip., , и . CODES+ISSS, стр. 481-490. ACM, (2009)Demonstration of a Time-predictable Flight Controller on a Multicore Processor., , , , , , и . ISORC, стр. 95-96. IEEE, (2019)An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip., , , и . SoC, стр. 171-174. IEEE, (2005)ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology., и . NOCS, стр. 55-64. IEEE Computer Society, (2008)Synthesis and layout of an asynchronous network-on-chip using Standard EDA tools., , , и . NORCHIP, стр. 1-6. IEEE, (2014)Interfacing hardware accelerators to a time-division multiplexing network-on-chip., , , и . NORCAS, стр. 1-4. IEEE, (2015)Asynchronous Circuit Design in Chisel Using Phase-Decoupled Click Elements., , и . DSD, стр. 168-175. IEEE, (2023)A Time-Predictable Memory Network-on-Chip., , , и . WCET, том 39 из OASIcs, стр. 53-62. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2014)Dynamic nsNET2: Efficient Deep Noise Suppression with Early Exiting., , , , , , , , и . MLSP, стр. 1-6. IEEE, (2023)A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling., , и . PATMOS, том 3254 из Lecture Notes in Computer Science, стр. 301-310. Springer, (2004)