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A High-Voltage Compliance, 32-Channel Digitally Interfaced Neuromodulation System on Chip.

, , , , , and . IEEE J. Solid State Circuits, 56 (8): 2476-2487 (2021)

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A hexagonal Field Programmable Analog Array consisting of 55 digitally tunable OTAs., , , , and . ISCAS, page 2897-2900. IEEE, (2008)Fundamental limits of jitter insensitivity in discrete and continuous-time sigma delta modulators., , and . ISCAS (1), page 1037-1040. IEEE, (2003)Multirate cascaded continuous time Sigma-Delta modulators., , , and . ISCAS (4), page 225-228. IEEE, (2002)Design issues and performance limitations of a clock jitter insensitive multibit DAC architecture for high-performance low-power CT Sigma Delta modulators., , and . ISCAS (1), page 1076-1079. IEEE, (2004)Frequency-Domain Analysis of Reconfigured Incremental ΔΣ ADCs on the Example of the Exponential Phase., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (11): 4346-4356 (November 2023)Delay Error Shaping in ΔΣ Modulators Using Time-Interleaved High Resolution Quantizers., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (7): 2700-2710 (July 2023)In Vitro Study of Artifact-Recovery Using a 32-Channel Neuromodulator Platform., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (9): 3474-3483 (September 2023)Live Demonstration: Designing CT BP ΣΔ Modulators with www.sigma-delta.de., and . ISCAS, page 1-. IEEE, (2018)An Arbiter PUF employing eye-opening oscillation for improved noise suppression., , and . ISCAS, page 1-5. IEEE, (2018)Incremental Sturdy-MASH Sigma-Delta Modulator with Reduced Sensitivity to DAC Mismatch., , , and . ISCAS, page 1-5. IEEE, (2019)