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Securing AI Hardware: Challenges in Detecting and Mitigating Hardware Trojans in ML Accelerators.

, , , , , , and . MWSCAS, page 821-825. IEEE, (2023)

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History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoring., , , , and . ISQED, page 498-505. IEEE, (2012)Reducing Execution Unit Leakage Power in Embedded Processors., and . SAMOS, volume 4017 of Lecture Notes in Computer Science, page 299-308. Springer, (2006)A+ Tuning: Architecture+Application Auto-Tuning for In-Memory Data-Processing Frameworks., , and . ICPADS, page 163-166. IEEE, (2019)Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks., , , , und . ISQED, Seite 499-507. IEEE, (2010)A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache)., , , und . CASES, Seite 251-260. ACM, (2009)Large Language Models for Code Analysis: Do LLMs Really Do Their Job?, , , , , , , , , und 1 andere Autor(en). CoRR, (2023)Deep Multi-attributed Graph Translation with Node-Edge Co-Evolution., , , , , und . ICDM, Seite 250-259. IEEE, (2019)DynGraph2Seq: Dynamic-Graph-to-Sequence Interpretable Learning for Health Stage Prediction in Online Health Forums., , , und . ICDM, Seite 1042-1047. IEEE, (2019)HybriDG: Hybrid Dynamic Time Warping and Gaussian Distribution Model for Detecting Emerging Zero-Day Microarchitectural Side-Channel Attacks., , , , und . ICMLA, Seite 604-611. IEEE, (2020)Stealthy Inference Attack on DNN via Cache-based Side-Channel Attacks., , , , , und . DATE, Seite 1515-1520. IEEE, (2022)