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A region-based theory for state assignment in speed-independent circuits.

, , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (8): 793-812 (1997)

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Incremental high-level synthesis., , , , , , and . ASP-DAC, page 701-706. IEEE, (2010)Coupling Asynchrony and Interrupts: Place Chart Nets., , , , , and . ICATPN, volume 1248 of Lecture Notes in Computer Science, page 328-347. Springer, (1997)A region-based theory for state assignment in speed-independent circuits., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (8): 793-812 (1997)Checking signal transition graph implementability by symbolic BDD traversal., , , , , and . ED&TC, page 325-332. IEEE Computer Society, (1995)Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis., , , , and . ASYNC, page 240-253. IEEE Computer Society, (1997)Realistic performance-constrained pipelining in high-level synthesis., , , and . DATE, page 1382-1387. IEEE, (2011)Exploiting area/delay tradeoffs in high-level synthesis., , , and . DATE, page 1024-1029. IEEE, (2012)Quasi-Static Scheduling for Concurrent Architectures., , , and . ACSD, page 29-40. IEEE Computer Society, (2003)Synthesis methodology for built-in at-speed testing., , and . ICCAD, page 183-188. IEEE Computer Society, (2005)Task generation and compile-time scheduling for mixed data-control embedded software., , , , , , , and . DAC, page 489-494. ACM, (2000)