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Understanding idle behavior and power gating mechanisms in the context of modern benchmarks on CPU-GPU Integrated systems.

, , , , and . HPCA, page 366-377. IEEE Computer Society, (2015)

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Exploring the Potential of Architecture-Level Power Optimizations., and . PACS, volume 3164 of Lecture Notes in Computer Science, page 132-147. Springer, (2003)Context-Sensitive Decoding: On-Demand Microcode Customization for Security and Energy Management., , and . IEEE Micro, 39 (3): 75-83 (2019)Heterogeneous Computing Guest editors' introduction., and . IEEE Micro, 35 (4): 4-5 (2015)Editorial: Special Section on CMP Architectures., and . IEEE Trans. Parallel Distributed Syst., 18 (8): 1025-1027 (2007)Introduction., and . ACM Trans. Archit. Code Optim., 2 (1): 1-2 (2005)Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy., , , and . MICRO, page 183-194. IEEE Computer Society, (2004)Control Flow Optimization Via Dynamic Reconvergence Prediction., , and . MICRO, page 129-140. IEEE Computer Society, (2004)Reducing power with dynamic critical path information., , and . MICRO, page 114-123. ACM/IEEE Computer Society, (2001)The CRISP performance model for dynamic voltage and frequency scaling in a GPGPU., and . MICRO, page 281-293. ACM, (2015)Pointer cache assisted prefetching., , , and . MICRO, page 62-73. ACM/IEEE Computer Society, (2002)