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CLA Formula Aided Fast Architecture Design for Clustered Look-Ahead Pipelined IIR Digital Filter.

, , , and . SiPS, page 60-66. IEEE, (2019)

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Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes., and . ISCAS (6), page 5786-5789. IEEE, (2005)Memory-reduced MAP decoding for double-binary convolutional Turbo code., , and . ISCAS, page 469-472. IEEE, (2010)A lightweight face detector by integrating the convolutional neural network with the image pyramid., , , and . Pattern Recognit. Lett., (2020)Hardware Accelerator Design for Sparse DNN Inference and Training: A Tutorial., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 71 (3): 1708-1714 (March 2024)FACCU: Enable Fast Accumulation for High-Speed DSP Systems., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (12): 4634-4638 (2022)Column-Weighted Probabilistic GDBF Decoder for Irregular LDPC Codes., , , and . ISVLSI, page 1-6. IEEE, (2023)An FPGA-Based Reconfigurable CNN Training Accelerator Using Decomposable Winograd., , , and . ISVLSI, page 1-6. IEEE, (2023)A Reconfigurable Accelerator for Generative Adversarial Network Training Based on FPGA., , , and . ISVLSI, page 144-149. IEEE, (2021)Automatic Generation of Dynamic Inference Architecture for Deep Neural Networks., , , , and . SiPS, page 117-122. IEEE, (2021)Segmented successive cancellation list polar decoding with joint BCH-CRC codes., , , , and . ACSSC, page 1509-1513. IEEE, (2017)