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Disambiguation of "Jiang, Jianfei"

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A Mapping Method for Reconfigurable Array based on Decoupled DataFlow.

, , , , , and . BigDataSecurity, page 180-185. IEEE, (2021)

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Jianfei Kralle

Jianfei Wang

Jianfei Wei

Qiu Jiang

Ping Jiang

 

Other publications of authors with the same name

Analog-to-digital converter based on single-electron tunneling transistors., , , and . IEEE Trans. Very Large Scale Integr. Syst., 12 (11): 1209-1213 (2004)Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (11): 2706-2717 (2015)A Hierarchical Communication Algorithm for Distributed Deep Learning Training., , , , , , and . MWSCAS, page 526-530. IEEE, (2023)Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture., , , , , and . DATE, page 124-129. IEEE, (2021)Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture., , , , , , , and . FPL, page 116-122. IEEE, (2023)Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable Array., , , , , , , and . ISCAS, page 1-5. IEEE, (2020)A CPU-FPGA Based Heterogeneous Accelerator for RepVGG., , , , , , and . ASICON, page 1-4. IEEE, (2021)Design of a high voltage stimulator chip for a stroke rehabilitation system., , , , , , , and . EMBC, page 834-837. IEEE, (2013)Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture., , , , , , and . DATE, page 1394-1399. IEEE, (2021)Boosting ReRAM-based DNN by Row Activation Oversubscription., , , , and . ASP-DAC, page 604-609. IEEE, (2022)