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Disambiguation of "Kim, Sang Yun"

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A 5.2 GHz RF Energy Harvester System Using Reconfigurable Parallel Rectenna.

, , , , , , , , and . MWSCAS, page 1-4. IEEE, (2018)

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Yun-sang Kim

Moo Sang Kim

Oh-Sang Kim

Sang-Kyum Kim

Sang Kyu Kim

 

Other publications of authors with the same name

Local Wavelets Decomposition for 3-D Surfaces., , , and . ICIP (4), page 357-360. IEEE, (1999)Reconfigurable ASIC Implementation of Asynchronous Recurrent Neural Networks., , , , , and . ASYNC, page 48-54. IEEE, (2021)Adaptive wavelets based multiresolution modeling of irregular meshes via harmonic maps., , and . ICIP (3), page 210-213. IEEE, (2001)A Multiresolution Wavelet Scheme for Irregularly Subdivided 3D Triangular Mesh., , , , and . ICIP (1), page 171-174. IEEE, (1999)An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques., , , , , , , , , and 18 other author(s). IEEE J. Solid State Circuits, 56 (1): 212-224 (2021)11-Bit 1.8uW 40KS/s segmented SAR ADC for sensor applications., , and . ISOCC, page 55-56. IEEE, (2016)A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power., , , , , , , , , and 20 other author(s). ISSCC, page 378-380. IEEE, (2019)22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process., , , , , , , , , and 29 other author(s). ISSCC, page 382-384. IEEE, (2020)BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 44 (11): 2987-2998 (2009)An Ultra Low Power, 3-Wire Serial Interface Design for Data Converters in Pin-Constrainted Applications with 180 nm CMOS Technology., , , , and . FIT, page 104-109. IEEE Computer Society, (2017)