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Supporting a Virtual Vector Instruction Set on a Commercial Compute-in-SRAM Accelerator., , , , , and . IEEE Comput. Archit. Lett., 23 (1): 29-32 (January 2024)PyH2: Using PyMTL3 to Create Productive and Open-Source Hardware Testing Methodologies., , , , , and . IEEE Des. Test, 38 (2): 53-61 (2021)Towards a Reconfigurable Bit-Serial/Bit-Parallel Vector Accelerator using In-Situ Processing-In-SRAM., , , , and . ISCAS, page 1-5. IEEE, (2020)Beyond Static Parallel Loops: Supporting Dynamic Task Parallelism on Manycore Architectures with Software-Managed Scratchpad Memories., , , , , , and . ASPLOS (3), page 46-58. ACM, (2023)Revisiting VerilogEval: Newer LLMs, In-Context Learning, and Specification-to-RTL Tasks., , , , and . CoRR, (2024)Layout-Based Evaluation of Read/Write Performance of SOT-MRAM and SOTFET-RAM., , , and . ESSDERC, page 283-286. IEEE, (2021)UMOC: Unified Modular Ordering Constraints to Unify Cycle- and Register-Transfer-Level Modeling., , , and . DAC, page 883-888. IEEE, (2021)PyHDL-Eval: An LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs., , , , and . MLCAD, page 10:1-10:17. ACM, (2024)Symbolic Elaboration: Checking Generator Properties in Dynamic Hardware Description Languages., , , and . MEMOCODE, page 126-136. ACM / IEEE, (2023)Implementing Low-Diameter On-Chip Networks for Manycore Processors Using a Tiled Physical Design Methodology., , and . NOCS, page 1-8. IEEE, (2020)