( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins.

, , , , , , и . CoRR, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Praveen Seshadri

Sangeetha Seshadri

Varadarajan Seshadri

Nagarajavel Vivekananthan

Vivek Venkataramani

 

Другие публикации лиц с тем же именем

Adaptive-Latency DRAM (AL-DRAM)., , , , , , и . CoRR, (2016)Exploiting Row-Level Temporal Locality in DRAM to Reduce the Memory Access Latency., , , , , , и . CoRR, (2018)Chapter Four - Simple Operations in Memory to Reduce Data Movement., и . Advances in Computers, (2017)Aksharantar: Towards building open transliteration tools for the next billion users., , , , , , , и . CoRR, (2022)RowClone: fast and energy-efficient in-DRAM bulk data copy and initialization., , , , , , , , , и 1 other автор(ы). MICRO, стр. 185-197. ACM, (2013)Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology., , , , , , , , , и . MICRO, стр. 273-287. ACM, (2017)Multilingual and code-switching ASR challenges for low resource Indian languages., , , , , , , , , и 12 other автор(ы). CoRR, (2021)MinUn: Accurate ML Inference on Microcontrollers., , , , и . CoRR, (2022)Shiftry: RNN inference in 2KB of RAM., , и . Proc. ACM Program. Lang., 4 (OOPSLA): 182:1-182:30 (2020)Mitigating Prefetcher-Caused Pollution Using Informed Caching Policies for Prefetched Blocks., , , , , , и . ACM Trans. Archit. Code Optim., 11 (4): 51:1-51:22 (2014)