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A Study of the Effect of RRAM Reliability Soft Errors on the Performance of RRAM-Based Neuromorphic Systems.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (11): 3125-3137 (2017)

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Design Space Exploration of Ovonic Threshold Switch (OTS) for Sub-Threshold Read Operation in Cross-Point Memory Arrays., and . ISCAS, page 1-5. IEEE, (2019)Design Considerations of Selector Device in Cross-Point RRAM Array for Neuromorphic Computing., , and . ISCAS, page 1-4. IEEE, (2018)1T2R: A novel memory cell design to resolve single-event upset in RRAM arrays., , , and . ASICON, page 12-15. IEEE, (2017)A highly reliable and tamper-resistant RRAM PUF: Design and experimental validation., , , , and . HOST, page 13-18. IEEE Computer Society, (2016)A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source With <6×10-6 Native Bit Error Rate., , , , , , , , , and 3 other author(s). ISSCC, page 402-404. IEEE, (2019)Benchmark of RRAM based Architectures for Dot-Product Computation., and . APCCAS, page 378-381. IEEE, (2018)A monolithic 3D design technology co-optimization with back-end-of-line oxide channel transistor., , and . NANOARCH, page 6:1-6:6. ACM, (2022)Enabling Long-Term Robustness in RRAM-based Compute-In-Memory Edge Devices., , and . ISCAS, page 1-5. IEEE, (2023)Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference Engine., , , and . MEMSYS, page 77-85. ACM, (2020)NeuroSim Validation with 40nm RRAM Compute-in-Memory Macro., , , , and . AICAS, page 1-4. IEEE, (2021)