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An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches.

, , and . ASPLOS, page 211-222. ACM Press, (2002)

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On-Chip Interconnection Networks of the TRIPS Chip., , , , , , and . IEEE Micro, 27 (5): 41-50 (2007)Fast Sort on CPUs, GPUs and Intel MIC Architectures, , , , , , and . Technical Report, Intel Labs, (2010)Can traditional programming bridge the ninja performance gap for parallel computing applications?, , , , , , , and . Commun. ACM, 58 (5): 77-86 (2015)Distributed Microarchitectural Protocols in the TRIPS Prototype Processor., , , , , , , , , and 7 other author(s). MICRO, page 480-491. IEEE Computer Society, (2006)Implementation and Evaluation of On-Chip Network Architectures., , , , and . ICCD, page 477-484. IEEE, (2006)A NUCA substrate for flexible CMP cache sharing., , , , , and . ICS, page 31-40. ACM, (2005)Building a Performance Model for Deep Learning Recommendation Model Training on GPUs., , , , , , , and . ISPASS, page 227-229. IEEE, (2022)Fast sort on CPUs and GPUs: a case for bandwidth oblivious SIMD sort., , , , , , and . SIGMOD Conference, page 351-362. ACM, (2010)Moguls: a model to explore the memory hierarchy for bandwidth improvements., , , , , , and . ISCA, page 377-388. ACM, (2011)Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU., , , , , , , , , and 2 other author(s). ISCA, page 451-460. ACM, (2010)