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A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management.

, , , , , , , , и . ISSCC, стр. 456-457. IEEE, (2009)

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Wei Wei

Wei Wei

Wei Wei

Wei Wei

Wei Wei

 

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Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits., , , , и . DAC, стр. 489-494. ACM Press, (1998)A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications., , , , , , , , , и 6 other автор(ы). ISSCC, стр. 324-606. IEEE, (2007)A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V., , , , , , , , , и 7 other автор(ы). ISSCC, стр. 212-214. IEEE, (2019)Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs., , и . VLSI Design, стр. 24-29. IEEE Computer Society, (2000)A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management., , , , , , , , и . ISSCC, стр. 456-457. IEEE, (2009)Design and optimization of dual-threshold circuits for low-voltage low-power applications., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 7 (1): 16-24 (1999)On effective IDDQ testing of low-voltage CMOS circuits using leakage control techniques., , и . IEEE Trans. Very Large Scale Integr. Syst., 9 (5): 718-725 (2001)Power minimization by simultaneous dual-Vth assignment and gate-sizing., , и . CICC, стр. 413-416. IEEE, (2000)High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness., , и . ICCD, стр. 227-232. IEEE Computer Society, (2000)A 0.094um2 high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist., , , , , и . VLSIC, стр. 266-. IEEE, (2015)