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Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis., , , , and . IET Comput. Digit. Tech., 3 (5): 398-412 (2009)A unified approach to constrained mapping and routing on network-on-chip architectures., , and . CODES+ISSS, page 75-80. ACM, (2005)Semi-Static Modulation Compression Optimization for Next Generation RANs., , , and . ICC, page 1-6. IEEE, (2021)Simulating DRAM controllers for future system architecture exploration., , , , and . ISPASS, page 201-210. IEEE Computer Society, (2014)Conservative application-level performance analysis through simulation of MPSoCs., , , and . ESTIMedia, page 51-60. IEEE Computer Society, (2010)Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip., , and . DATE, page 954-959. EDA Consortium, San Jose, CA, USA, (2007)Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip., , and . CODES+ISSS, page 149-154. ACM, (2007)A Monitoring-Aware Network-on-Chip Design Flow., , , and . DSD, page 97-106. IEEE Computer Society, (2006)CoMPSoC: A template for composable and predictable multi-processor system on chips., , , and . ACM Trans. Design Autom. Electr. Syst., 14 (1): 2:1-2:24 (2009)Modulation Compression in Next Generation RAN: Air Interface and Fronthaul trade-offs., , , and . CoRR, (2020)