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Disambiguation of "Udipi, Aniruddha N."

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Simulating DRAM controllers for future system architecture exploration.

, , , , and . ISPASS, page 201-210. IEEE Computer Society, (2014)

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Aniruddha Nazre

Aniruddha Marathe

Aniruddha Kembhavi

Aniruddha Jayant Deshpande

 

Other publications of authors with the same name

CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems., , , , , , , , , and 3 other author(s). ISCA, page 39:1-39:17. ACM, (2023)Designing Efficient Memory for Future Computing Systems.. University of Utah, USA, (2012)Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy., , , , , , , and . HPCA, page 262-274. IEEE Computer Society, (2009)Simulating DRAM controllers for future system architecture exploration., , , , and . ISPASS, page 201-210. IEEE Computer Society, (2014)Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device., , , , , and . MICRO, page 198-209. ACM, (2013)Rethinking DRAM design and organization for energy-constrained multi-cores., , , , , and . ISCA, page 175-186. ACM, (2010)LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems., , , , and . ISCA, page 285-296. IEEE Computer Society, (2012)Non-uniform power access in large caches with low-swing wires., , and . HiPC, page 59-68. IEEE Computer Society, (2009)Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems., , , , and . ISCA, page 425-436. ACM, (2011)Towards scalable, energy-efficient, bus-based on-chip networks., , and . HPCA, page 1-12. IEEE Computer Society, (2010)