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Multi-Corner Parametric Yield Estimation via Bayesian Inference on Bernoulli Distribution with Conjugate Prior.

, , , , , and . ISCAS, page 1-4. IEEE, (2020)

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An automatic clock tree design system for high-speed VLSI designs: planar clock routing with the treatment of obstacles., and . ISCAS (6), page 258-261. IEEE, (1999)FMSSQP: An efficient global optimization tool for the robust design of Rail-to-Rail Op-Amp., , , and . ASICON, page 1-4. IEEE, (2013)Efficient SVM-based hotspot detection using spectral clustering., , , and . ISCAS, page 1-4. IEEE, (2017)Optimization of VLSI Allocation., and . ISCAS, page 1065-1068. IEEE, (1995)Propagation Delay in RLC Interconnection Networks., and . ISCAS, page 2125-2128. IEEE, (1993)Frequency driven repeater insertion for deep submicron., , , and . ISCAS (5), page 181-184. IEEE, (2004)RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect., , , and . ISCAS, page 2710-2713. IEEE, (2007)Correlated Rare Failure Analysis via Asymptotic Probability Evaluation., , , , , and . DAC, page 54:1-54:6. ACM, (2017)Efficient Spatial Variation Modeling of Nanoscale Integrated Circuits Via Hidden Markov Tree., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (6): 971-984 (2016)Batch Bayesian Optimization via Multi-objective Acquisition Ensemble for Automated Analog Circuit Design., , , , and . ICML, volume 80 of Proceedings of Machine Learning Research, page 3312-3320. PMLR, (2018)