( en | de | ru )

 

Disambiguation of "Garg, Rajesh"

Author of the publication

copydeleteadd this publication to your clipboard
A lithography-friendly structured ASIC design approach.

, , , and . ACM Great Lakes Symposium on VLSI, page 315-320. ACM, (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Neil Garg

Rajesh Saiju

Hybrid Power System Modelling - Simulation and Energy Management Unit Development. Uni Kassel, (2008)

Animesh Garg

Rajesh Chitta

Martin Garg

 

Other publications of authors with the same name

A lithography-friendly structured ASIC design approach., , , and . ACM Great Lakes Symposium on VLSI, page 315-320. ACM, (2008)A robust, fast pulsed flip-flop design., , and . ACM Great Lakes Symposium on VLSI, page 119-122. ACM, (2008)A methodology for interconnect dimension determination., , and . ISPD, page 189-195. ACM, (2007)Circuit-Level Design Approaches for Radiation-Hard Digital Electronics., , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (6): 781-792 (2009)On the Improvement of Statistical Static Timing Analysis., , and . ICCD, page 37-42. IEEE, (2006)A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements., , and . DATE, page 354-359. ACM, (2008)A PLA based asynchronous micropipelining approach for subthreshold circuit design., , , and . DAC, page 419-424. ACM, (2006)Low power and high performance sram design using bank-based selective forward body bias., , , and . ACM Great Lakes Symposium on VLSI, page 441-444. ACM, (2009)Pipelined network of PLA based circuit design., , and . ACM Great Lakes Symposium on VLSI, page 213-218. ACM, (2008)Selective Forward Body Bias for High Speed and Low Power SRAMs., , , and . J. Low Power Electron., 5 (2): 185-195 (2009)