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Disambiguation of "Garg, Rajesh"

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Circuit-Level Design Approaches for Radiation-Hard Digital Electronics.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (6): 781-792 (2009)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Neil Garg

Rajesh Saiju

Hybrid Power System Modelling - Simulation and Energy Management Unit Development. Uni Kassel, (2008)

Animesh Garg

Rajesh Chitta

Priya Garg

 

Other publications of authors with the same name

A methodology for interconnect dimension determination., , and . ISPD, page 189-195. ACM, (2007)Circuit-Level Design Approaches for Radiation-Hard Digital Electronics., , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (6): 781-792 (2009)A lithography-friendly structured ASIC design approach., , , and . ACM Great Lakes Symposium on VLSI, page 315-320. ACM, (2008)A robust, fast pulsed flip-flop design., , and . ACM Great Lakes Symposium on VLSI, page 119-122. ACM, (2008)A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements., , and . DATE, page 354-359. ACM, (2008)On the Improvement of Statistical Static Timing Analysis., , and . ICCD, page 37-42. IEEE, (2006)A fast, analytical estimator for the SEU-induced pulse width in combinational designs., , and . DAC, page 918-923. ACM, (2008)A design flow to optimize circuit delay by using standard cells and PLAs., , , , , and . ACM Great Lakes Symposium on VLSI, page 217-222. ACM, (2006)3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit., and . ICCD, page 498-504. IEEE Computer Society, (2009)Low Power UWB Transceiver Design Using Dynamic Voltage Scaling., , , and . WCNC, page 1757-1762. IEEE, (2007)