( en | de | ru )

 

Disambiguation of "Jang, Sungchun"

Author of the publication

copydeleteadd this publication to your clipboard
A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Gm Bias.

, , , , , , , , and . IEEE J. Solid State Circuits, 51 (10): 2312-2327 (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Tae-Seok Jang

Liem Khiem Jang

Saeed Jangani

Eun-Ju Jang

Hee-Kwon Jang

 

Other publications of authors with the same name

An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (9): 836-840 (2015)An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation., , , , , and . VLSIC, page 136-. IEEE, (2015)A compact 22-Gb/s transmitter for optical links with all-digital phase-locked loop., , , , , and . ISCAS, page 2856-2859. IEEE, (2015)A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection., , , , , , , , , and . ESSCIRC, page 384-387. IEEE, (2015)A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm., , , , , , , , and . A-SSCC, page 1-4. IEEE, (2015)A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Gm Bias., , , , , , , , and . IEEE J. Solid State Circuits, 51 (10): 2312-2327 (2016)A 13.8mW 3.0Gb/s clock-embedded video interface with DLL-based data-recovery circuit., , , and . ISSCC, page 450-452. IEEE, (2011)A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme., , , , , , , , , and 25 other author(s). ISSCC, page 380-382. IEEE, (2019)22.6 A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface., , , , and . ISSCC, page 340-342. IEEE, (2020)