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Disambiguation of "Cho, Sung-Yong"

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A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Gm Bias.

, , , , , , , , and . IEEE J. Solid State Circuits, 51 (10): 2312-2327 (2016)

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Sung-Yong Cho

Sung-Jun Cho

Gyu-Sung Cho

Sung-bok Cho

In-Sung Cho

 

Other publications of authors with the same name

A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology., , , , , , , , , and 27 other author(s). ISSCC, page 430-432. IEEE, (2012)29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration., , , , , , , and . ISSCC, page 494-495. IEEE, (2017)A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line., , , , , and . ESSCIRC, page 447-450. IEEE, (2014)Convolutional-Neural-Network-Based Partial Discharge Diagnosis for Power Transformer Using UHF Sensor., , , , and . IEEE Access, (2020)A theoretical analysis of phase shift in pulse injection-locked oscillators., , , , , and . ISCAS, page 1662-1665. IEEE, (2016)A new micro biological cell injection system., and . IROS, page 1642-1647. IEEE, (2004)A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop., , , , and . A-SSCC, page 73-76. IEEE, (2018)13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration., , , , , , , , , and 25 other author(s). ISSCC, page 242-244. IEEE, (2024)256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers., , , , , , , , , and 19 other author(s). IEEE J. Solid State Circuits, 52 (1): 210-217 (2017)A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Gm Bias., , , , , , , , and . IEEE J. Solid State Circuits, 51 (10): 2312-2327 (2016)