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Disambiguation of "Rajendran, Bipin"

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Hybrid In-Memory Computing Architecture for the Training of Deep Neural Networks.

, , , and . ISCAS, page 1-5. IEEE, (2021)

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Chitra Rajendran

Vidyalakshmi Rajendran

Bipin Juthani

Ranjithkumar Rajendran

Lawrence Rajendran

 

Other publications of authors with the same name

Acceleration of Convolutional Networks Using Nanoscale Memristive Devices., , and . EANN, volume 893 of Communications in Computer and Information Science, page 240-251. Springer, (2018)Training Probabilistic Spiking Neural Networks with First-to-spike Decoding., , and . CoRR, (2017)Live Demonstration: Image Classification Using Bio-inspired Spiking Neural Networks., , and . ISCAS, page 1-. IEEE, (2018)Nanoscale electronic synapses using phase change devices., , , , , , , , , and 5 other author(s). JETC, 9 (2): 12:1-12:20 (2013)Training Multilayer Spiking Neural Networks using NormAD based Spatio-Temporal Error Backpropagation., and . CoRR, (2018)Mimicking the worm - An adaptive spiking neural circuit for contour tracking inspired by C. Elegans thermotaxis., , and . IJCNN, page 2079-2086. IEEE, (2014)C. elegans chemotaxis inspired neuromorphic circuit for contour tracking and obstacle avoidance., and . IJCNN, page 1-8. IEEE, (2015)NormAD - Normalized Approximate Descent based supervised learning rule for spiking neurons., and . IJCNN, page 1-8. IEEE, (2015)Arithmetic computing via rate coding in neural circuits with spike-triggered adaptive synapses., and . IJCNN, page 1-8. IEEE, (2015)Low-Power Neuromorphic Hardware for Signal Processing Applications: A review of architectural and system-level design approaches., , , , and . IEEE Signal Process. Mag., 36 (6): 97-110 (2019)