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Disambiguation of "sun Seo, Jae"

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Hybrid In-Memory Computing Architecture for the Training of Deep Neural Networks.

, , , and . ISCAS, page 1-5. IEEE, (2021)

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Sun-Aea Seo

Sun-Jae Lee

Sun-Jae Song

Jae-Sun Kim

Jae Sun Gross-Lee

 

Other publications of authors with the same name

In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter., , , , , , and . ISSCC, page 188-189. IEEE, (2010)Cases for Analog Mixed Signal Computing Integrated Circuits for Deep Neural Networks., , , , and . VLSI-DAT, page 1-2. IEEE, (2019)Fully-integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS., , , , and . ISLPED, page 140-145. IEEE, (2015)A 8.93-TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity With All Parameters Stored On-Chip., , , and . ESSCIRC, page 119-122. IEEE, (2019)Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access., and . CICC, page 1-4. IEEE, (2020)An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays., , , and . DATE, page 1019-1024. IEEE, (2020)FP-IMC: A 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro., , , , , and . ESSCIRC, page 405-408. IEEE, (2023)A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification., , , , , , , , and . ESSCIRC, page 89-92. IEEE, (2022)An Energy-Efficient Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access., and . IEEE J. Solid State Circuits, 56 (3): 803-813 (2021)Big-Little Chiplets for In-Memory Acceleration of DNNs: A Scalable Heterogeneous Architecture., , , , , , , and . ICCAD, page 8:1-8:9. ACM, (2022)